module ALU(
  input       [2:0]   ALUctrl,
  input       [31:0]  data1_in,
  input       [31:0]  data2_in,

  output  reg [31:0]  data,
  output  reg         zero_flag
);


always @(data1_in or data2_in or ALUctrl) begin
  // ALUctrl = 010 (add, lw, sw)
  if (~ALUctrl[2] & ALUctrl[1] & ~ALUctrl[0]) begin
    data = data1_in + data2_in;
    if (data == 32'b0)  zero_flag = 1'b1;
    else                zero_flag = 1'b0;
  end

  // ALUctrl = 110 (sub, beq)
  if (ALUctrl[2] & ALUctrl[1] & ~ALUctrl[0]) begin
    data = data1_in - data2_in;
    if (data == 32'b0)    zero_flag = 1'b1;
    else                  zero_flag = 1'b0;
  end

  // ALUctrl = 000 (and)
  if (~ALUctrl[2] & ~ALUctrl[1] & ~ALUctrl[0]) begin
    data = data1_in & data2_in;
    if (data == 32'b0)    zero_flag = 1'b1;
    else                  zero_flag = 1'b0;
  end

  // ALUctrl = 001 (or)
  if (~ALUctrl[2] & ~ALUctrl[1] & ALUctrl[0]) begin
    data = data1_in | data2_in;
    if (data == 32'b0)    zero_flag = 1'b1;
    else                  zero_flag = 1'b0;
  end

  // ALUctrl = 111 (slt) -- zero_flag = don't care.
  if (ALUctrl[2] & ALUctrl[1] & ALUctrl[0]) begin
    if ((data1_in - data2_in) < 0)  data = 32'b1;
    else data = 32'b0;
  end
end

endmodule